Sipeed Tang Primer: GOWIN GW2A FPGA GoAI Development Board Kit with LvDs interface, BSRAM Resources, 1GB DDR3, and RISC-V Code

-Specification- Brand Name: Sipeed Demo Board Type: Tang Primer 20K Core Module Memory: 128M DDR3, 13Row x 10Col x 8banks x 16bits Flash: 32Mbits NOR Flash, W25Q32JVS Debugger: Jtag + Uart, JST SH1.0 8Pins connector SD card slot: Push-pull type Display: 8Pins spi lcd connector Package: 204P DDR3 Avaliable IO: 117 RGB Interface: 1x RGB565 40P FPC Connector DVP Interface: 1x 24P FPC Connector Mic array Interface: 1x 10P FPC Connector Touch Interface: 1x 4P FPC Connector PMOD Interface: 43.5mm Headphone Jack: 1x LPA4809MSF driver DIP switch: 1x 5P DIP switch Slide switch: 1x Switch USB function: High-performance DSP

The Sipeed Tang Primer 20K Core Module is a sodimm package board that uses the GW2A-LV18PG256C8I7 as the main chip, featuring multiple internal resources including high-performance DSP, high-speed LvDs interface, BSRAM resources, onboard DDR3, and PMIC. This allows users to use the CM board for rapid development and verification, making it suitable for high-speed and low-cost situations.

Users also have the capability to burn the hardware code bitstream file of PicoRV/Litex to GW2A, and then use GW2A as a common MCU. This enables the running of RISC-V code and the conducting of RISC-v soft core experiments.

Additionally, users can utilize Verilog to design custom hardware functions based on the PicoRV/Litex IP core, while simultaneously using C language to write code running on the PicoRV/Litex core.

The Sipeed Tang Primer 20K Dock is equipped with a variety of peripheral resources, including onboard USB-JTAG & UART peripheral, Ethernet PHY and RJ45 connector, USB2.0 PHY, HDMI output connector, audio output circuit and 3.5mm connector, RGB screen connector, and DVP camera connector.

Furthermore, the Sipeed Tang Primer 20K Lite ext-board routes numerous IOs to double row pin headers and PMOD interfaces, providing users with the ability to easily connect other peripheral modules or circuits for secondary development.

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