Sipeed Tang Primer 20K Lite Ext-board GOWIN GW2A FPGA GoAI Core Board

-Specification- Brand Name: MaixPyDemo Type: FPGA Development Board Memory: 128MB DDR3 SODIMM, 13Row x 10Col x 8banks x 16bits Flash: 32Mbits NOR Flash, W25Q32JVS Debugger: Jtag + Uart, JST SH1.0 8Pins connector SD card slot: Push-pull type Display: 8Pins spi lcd connector Package: 204P DDR3 Available IO: 117 RGB Interface: 1x RGB565 40P FPC Connector DVP Interface: 1x 24P FPC Connector Mic array Interface: 1x 10P FPC Connector Touch Interface: 1x 4P FPC Connector PMOD Interface: 43.5mm headphone Jack: 1x LPA4809MSF driver DIP switch: 1x 5P DIP switch Slide switch: 1x Switch USB function

-Package Content- 1x Sipeed Tang Primer 20K Lite ext-board 1x Sipeed Tang Primer 20K Core Broad 1x RV debugger plus 1x Type-C Data Cable 1x 8P 1.0mm to 2.54mm Terminal wires

-Technical Support- Please click "WayPonDEV" and ask a question. Please leave a message monica#smartfire.cn (f------>@) skype: monica_9122. Please leave a message in our forum by forum.youyeetoo.com/.

👍[High-performance DSP] The Sipeed Tang Primer 20K Core Module board is in a sodimm package, and it uses GW2A-LV18PG256C8I7 as the main chip. It has multiple internal resources, such as high-performance DSP, high-speed LvDs interface, BSRAM resources, on-board DDR3, and PMIC. Users could use this CM board for rapid development and verification, and it's suitable for high-speed and low-cost situations.

👍[Run RISC-V Code] Users can burn the hardware code bitstream file of PicoRV/Litex to Gw2A, and then use GW2A as a common MCU. It can run RISC-V code and conduct RISC-v soft core experiments.

👍[Verilog Design] Users can use Verilog to design custom hardware functions based on the PicoRV/Litex lP core, and at the same time use C language to write code running on PicoRV/Litex core.

👍[Rich Peripheral interfaces] The Sipeed Tang Primer 20K Dock is equipped with a wealth of peripheral resources, such as onboard USB-JTAG & UART peripheral, Ethernet PHY and RJ45 connector, USB2.0 PHY, HDMI output connector, Audio output circuit and 3.5mm connector, RGB screen connector, and DVP camera connector.

👍[PMOD interfaces] The Sipeed Tang Primer 20K Lite ext-board routes so many IOs to double row pin headers and PMOD interfaces, with which users could easily connect other peripheral modules or circuits for secondary development.

👍[Minimalist IDE] Compared with other FPGA IDE, the IDE used to develop Tang Primer 20K is really small, the hard disk capacity occupied after installation does not exceed 1G.

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